82443LX Datasheet, PDF (42/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Bit
Description
5 MDA Present—R/W. This bit works with the VGA Enable bit in the BCTRL register of device 1 to
control the routing of CPU initiated transactions targeting MDA compatible I/O and memory
address ranges. When the VGA Enable bit is set to 1, and this bit is reset to 0, references to MDA
resources are sent to A.G.P. In all other cases references to MDA resources are sent to PCI.
MDA resources are defined as the following:
Memory:
0B0000h–0B7FFFh
I/O:
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to
PCI even if the reference includes I/O locations not listed above.
The following table shows the behavior for all combinations of the MDA present and VGA forward
bits:
VGA MDA Behavior
0
0
All references to MDA and VGA go to PCI
0
1
Reserved
1
0
All references to VGA go to A.G.P.—MDA-only
(I/O 3BFh and aliases) references go to PCI
1
1
VGA references go to A.G.P.; MDA references go to PCI
4:0 Reserved.
3.3.13. DBC—DATA BUFFER CONTROL REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
53h
83h
Read/Write
This 8-bit register allows for PAC buffer control.
Bit
Description
7 Reserved.
6 CPU-to-PCI IDE Posting Enable (CPIE).
1=Enable.
0=Disable (default). When disabled, the cycles are treated as normal I/O write transactions.
5 WC Write Post During I/O Bridge Access Enable (WPIO).
1 = Enable. When enabled, posting of WC transactions to PCI occur, even if the I/O bridge has
been granted access to the PCI bus via corresponding arbitration and buffer management
protocol (PHLD#/PHLDA#/WSC#).
0 = Disable (default).
NOTE
USWC Write posting should only be enabled if a USWC region is located on the PCI bus.
4:0 Reserved.
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