82443LX Datasheet, PDF (94/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
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4.3.3. REFRESH CYCLES (CAS# BEFORE RAS#)
PAC supports CAS#-before-RAS# DRAM refresh cycles and generates refresh requests. When a refresh
request is generated, it is placed in a 4 entry queue (this queue can be disabled in the DRAM Control
Register, offset 57h, bit 6). PAC services a refresh request when the refresh queue is not empty and the
controller has no other requests pending. When the refresh queue has accumulated four requests, refresh
becomes the highest priority request and is serviced next by PAC.
PAC implements a “smart refresh” algorithm. Refresh is only performed on rows that are populated. In
addition, PAC supports refresh staggering to minimize the power surge associated with refreshing a large
DRAM array. PAC also supports concurrent refresh cycles in parallel with Host to A.G.P. or PCI cycles.
4.3.4. DRAM SUBSYSTEM POWER MANAGEMENT
PAC supports desktop-level power management capability. The DRAM controller within PAC supports power
management of the DRAM array. Specific power management capability is engaged only when the memory
array is populated with SDRAM (this includes mixed EDO/SDRAM memory array configurations), and the
SPME bit of the DRAMC Register is set (bit 4 of configuration address 57h). The DRAM power management
operates as follows:
PAC enters the SUSPEND state when:
• The SPME bit of the DRAMC Register is set (bit 4 of configuration address 57h).
• PAC completes all pending requests from all request queues, including the refresh queue.
• PAC closes active SDRAM pages according to PAC DRAM Paging Policy.
a. After 4 Host clocks upon entering this state, the SDRAM CKE signal is negated and all memory rows
populated with SDRAM enter a Power Down Mode.
b. PAC remains in the SUSPEND state until any request, other than a low priority Refresh request, is
pending.
c. When in the SUSPEND regime, refresh requests are not serviced until they become a high-priority,
i.e., 4 requests are queued.
d. When a high-priority refresh request is generated (4th request queued), the DRAM controller asserts
CKE. Four clocks after CKE is reasserted, the DRAM controller starts servicing refresh requests.
Refreshes are serviced back-to-back (all four of them) until the refresh request queue is empty.
e. Four clocks after reaching Idle state the DRAM controller negates CKE again (SDRAM components
enter Power Down Mode again). The system stays in this state until 4 refresh requests are
accumulated (typically after 4*15.6 µsec) and then PAC repeats steps 3 & 4.
The SUSPEND state is exited normally after any of the snoopable or non-snoopable request queues present
an active request.
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