82443LX Datasheet, PDF (18/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Signal
SRAS3# /
MAB5
SCAS[2:0]#
SCAS3# /
MAB4
Table 2. DRAM Interface Signals
Type
Description
O
LVTTL
Configuration #1:
SDRAM Row Address Strobe 3 (SDRAM): The SRAS3# signal is a copy
(for loading purposes) of the same logical SRASx signal. It generates SDRAM
commands encoded on SRASx/SCASx/WE signals. When SRASx is sampled
active at the rising edge of the SDRAM clock, the row address is latched into the
SDRAMs.
Configuration #2:
Extra Copy of Memory Address 5 (EDO/SDRAM): MAB[5] is an extra copy of
Memory Address 5 and should be routed to the closest DIMM socket to the
PAC(socket #0). MAB5 will change value if the current or next access is directed
to a memory address range mapped to DIMM socket #0. During accesses
directed to DIMM socket #1 or #2, these signals will preserve the previously
driven state. This signal behaves logically and electrically the same way as
MAA5.
These signals have programmable buffer strengths for optimization under different
signal loading conditions.
O
LVTTL
SDRAM Column Address Strobe (SDRAM): The SCAS[2:0]# signals are
multiple copies (for loading purposes) of the same logical SCASx signal used to
generate SDRAM commands. These commands are encoded on
SRASx/SCASx/WE signals. When SCASx is sampled active at the rising edge of
the SDRAM clock, the column address is latched into the SDRAMs.
Same function for Configuration #1 and Configuration #2.
These signals have programmable buffer strengths for optimization under different
signal loading conditions.
O
LVTTL
Configuration #1:
SDRAM Column Address Strobe 3 (SDRAM): The SCAS3# signal is a physical
copy (for loading purposes) of the same logical SCASx signal used to generate
SDRAM command encoded on SRASx/SCASx/WE signals. When SCASx is
sampled active at the rising edge of the SDRAM clock, the column address is
latched into the SDRAMs. These signals drive the SDRAM array directly without
any external buffers.
Configuration #2:
Extra Copy of Memory Address 4 (EDO/SDRAM): MAB[4] is an extra copy of
Memory Address 4 and should be routed to the closest DIMM socket to the
PAC(socket #0). MAB4 will change value if the current or next access is directed
to a memory address range mapped to DIMM socket #0. During accesses
directed to DIMM socket #1 or #2, these signals will preserve the previously
driven state. This signal behaves logically and electrically the same way as
MAA4.
These signals have programmable buffer strengths for optimization under different
signal loading conditions.
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