82443LX Datasheet, PDF (102/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
FRAME# Protocol Operations on A.G.P.
The A.G.P. Interface supports FRAME# protocol operations similar to those defined in the PCI Specification.
Electrically, only 66-MHz FRAME# protocol operations are supported.
• Host Bridge Target Operations. As a target of FRAME#-initiated cycles via A.G.P., PAC responds only
to memory accesses. These accesses are always directed to DRAM.
 Memory Read, Memory Read Line, Memory Read Multiple Operations. PAC only responds to
memory read cycles that target DRAM space. Reads to the PCI bus from an A.G.P. device are not
supported.
 Memory Write, Memory Write and Invalidate Operations. PAC responds to FRAME#-initiated
memory writes that target either the DRAM space or the PCI Bus space.
 Configuration Read and Write Operations. A.G.P. generated configuration cycles are ignored
by PAC.
 PAC Disconnect Conditions. PAC generates disconnect according to the A.G.P. Specification rules
when being accessed as a target from the A.G.P. interface (using FRAME# protocol). The A.G.P.
transaction issued using FRAME# semantics is retried by PAC based on the 32-clock rule only if
there is a pending A.G.P.-to-DRAM request issued using A.G.P. protocol semantics (using PIPE# or
side-band request).
 PAC Retry Conditions. In the absence of A.G.P. requests, a FRAME#-initiated request is kept in
wait states until it gets serviced or potentially retried due to buffer management requirements (i.e.,
CPU-to-A.G.P. writes occurs before A.G.P.-to-DRAM snoopable read gets serviced). PAC, as an
A.G.P. target, retries the initial data phase of the FRAME#-initiated access when:
• PAC’s DRAM is locked from the CPU side or by an agent on the PCI Bus.
• There is a CPU-to-A.G.P. posted write data that must be flushed before PAC can service A.G.P.
PCI-to-DRAM reads. This also includes CPU-to-A.G.P. deferred writes.
If, after completing the initial data phase, it takes longer than 8 A.G.P. clock periods to complete the
particular data phase, the consecutive data phase(s) are disconnected.
 Fast Back-to-Back Transactions. PAC, as a target, accepts fast back-to-back cycles from the
A.G.P. master accessing different agents during a back-to-back sequence. As an initiator, PAC does
not generate a fast back-to-back cycle.
 Delayed Transaction. When an A.G.P.-to-DRAM read cycle is retried by PAC, it will be processed
internally as a Delayed Transaction. PAC supports the Delayed Transaction mechanism on the
A.G.P. interface as defined in the A.G.P. Specification.
• Host Bridge Initiator Operations. PAC translates valid CPU bus commands and PCI Bus write cycles
destined to the A.G.P. bus into A.G.P. bus requests. For all CPU-to-A.G.P. transactions, PAC is a non-
caching agent since PAC does not support cacheability on the A.G.P. Bus. However, PAC must respond
appropriately to the CPU bus commands that are cache oriented. PAC will forward writes from the PCI
bus to the A.G.P. Bus.
• PCI Compatibility and Restrictions. The A.G.P. Bus interface implementation is compatible with A.G.P.
Specification, Revision 1.0. Transactions that are crossing from the A.G.P. Bus to the PCI Bus are limited
only to memory writes.
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