82443LX Datasheet, PDF (16/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Table 2. DRAM Interface Signals
Signal
Type
Description
RCSA[7:6]# /
MAB[3:2]
O
LVTTL
Configuration #1:
Row Address Strobe 7-6 (EDO): These signals are used to latch the row
address into the memory array. Each signal is used to select one DRAM row.
These signals drive the DRAM array directly without any external buffers.
Chip Select 7-6 (SDRAM): For the memory row configured with SDRAM, these
pins perform the function of selecting the particular SDRAM components during
the active state.
Configuration #2:
Extra Copy of Memory Address 3-2 (EDO/SDRAM): MAB[3:2] are extra copies
of Memory Address [3:2] and should be routed to the closest DIMM socket to the
PAC(socket #0). MAB[3:2] will change value if the current or next access is
directed to a memory address range mapped to DIMM socket #0. During
accesses directed to DIMM socket #1 or #2, these signals will preserve the
previously driven state. These signals behave logically and electrically the same
way as MAA[3:2].
These signals have programmable buffer strengths for optimization under different
signal loading conditions.
RCSB[7:0]# /
MAB[13:6]
O
LVTTL
Configuration #1:
Extra copy of Row Address Strobe 7-0 (EDO): These signals are used to latch
the row address into the memory array. Each signal is used to select one DRAM
row. These signals drive the DRAM array directly without any external buffers.
Extra Copy of Chip Select 7-0 (SDRAM): For the memory row configured with
SDRAM, these pins perform the function of selecting the particular SDRAM
components during the active state.
Configuration #2:
Extra Copy of Memory Address 13-6 (EDO/SDRAM): MAB[13:6] are extra
copies of Memory Address [13:6] and should be routed to the closest DIMM
socket to the PAC(socket #0). MAB[13:6] will change value if the current or next
access is directed to a memory address range mapped to DIMM socket #0.
During accesses directed to DIMM socket #1 or #2, these signals will preserve
the previously driven state. These signals behave logically and electrically the
same way as MAA[13:6].
These signals have programmable buffer strengths for optimization under different
signal loading conditions.
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