82443LX Datasheet, PDF (59/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
3.3.26. ERRSTS1—ERROR STATUS REGISTER 1 (DEVICE 0)
Address Offset:
Default Value:
Access:
Size:
92h
00h
Read Only, Read/Write Clear
8 bits
This 8-bit register is used to report A.G.P. error conditions. SERR# is generated on a zero to one transition of
any of these flags (if enabled by the ERRCMD register).
Bit
Description
7:3 Reserved
2 A.G.P. non-snoopable access outside of Graphics Aperture.
1=Indicates that an A.G.P. access occurred to the address that is outside of the graphics
aperture range. Software has to write 1 to clear this bit.
1 A.G.P. non-snoopable access to the location outside of main DRAM ranges and aperture
range. Software has to write a 1 to clear this bit.
1=Indicates that an A.G.P. read access is not destined for main DRAM ranges (visible from
A.G.P.) or to the aperture.
PAC guarantees that the first access outside of DRAM will always receive a SERR# (provided the
feature is enabled). SERR# may or may not be asserted for subsequent accesses outside DRAM
depending on the delay between the abnormal cycles.
0 Access to Invalid Graphics Aperture Translation Table Entry(AIGATT)(R/WC). Software has
to write a 1 to clear this bit.
1=Indicates that DRAM access to aperture resulted in an invalid translation table entry.
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