82443LX Datasheet, PDF (143/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

E
INTEL 82443LX (PAC)
8.1.1. NAND CHAIN TEST MODE
This test mode is used during board level connectivity test. This allows ATE to test the connectivity of PAC
signal pins. Special attention should be taken to channel sharing, and the NAND chain element assignment,
so that signal sharing the same tester channel don’t end up on the same chain.
Table 38. NAND Chain Outputs
Pins for NAND Chain
Purpose
SBA[0]
NAND Chain 0 Output
SBA[1]
NAND Chain 1 Output
SBA[2]
NAND Chain 2 Output
SBA[3]
NAND Chain 3 Output
SBA[4]
NAND Chain 4 Output
SBA[5]
NAND Chain 5 Output
SBA[6]
NAND Chain 6 Output
SBA[7]
NAND Chain 7 Output
The 82443LX NAND chain pin assignments are shown in the table below:
Table 39. The 82443LX NAND Chain Pin Assignments
NANDtree0 NANDtree1 NANDtree2 NANDtree3 NANDtree4 NANDtree5 NANDtree6 NANDtree7
GAD24
GAD21
GAD30
GAD25
SBSTB
MECC4 GREQ#
A10
GAD20
GAD29
GAD28
GAD27 ADSTB_B MECC5 GC/BE3#
A7
GAD22
GAD23
GAD26
GAD31 GDEVSEL SCAS0# GC/BE2#
A8
GAD18
GAD17
MD0
MD34 ADSTB_A SCAS1# GFRAME
A14
GAD16
GAD19
MD5
MD32
MECC0
WE1#
GPAR#
A12
GAD12
GAD11
MD1
MD37
SRAS1#
WE3#
GPERR#
A13
GAD8
GAD15
MD2
MD33
CDQA1# SCAS2# GSERR#
A16
GAD10
GAD5
MD3
MD35
MECC1 CDQA4# GIRDY#
A19
GAD14
GAD13
MD7
MD36
CDQA0# CDQB5# GSTOP#
A11
GAD4
GAD9
MD6
MD40
WE0#
CDQB1# GTRDY#
A21
GAD0
GAD7
MD4
MD39
WE2#
SCAS3# GC/BE0#
A18
GAD2
GAD1
MD8
MD38
CDQA5# RCSB1# GC/BE1#
A20
GAD6
GAD3
MD14
MD42
SRAS0# RCSB3#
RBF#
A22
HD5
HD32
MD9
MD41
SRAS2# RCSB4#
PIPE#
A17
HD9
HD39
MD10
MD45
RCSA6# RCSB7#
CKE
A26
HD2
HD43
MD15
MD44
RCSA7# RCSB5# ECCERR
A15
143