82443LX Datasheet, PDF (71/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
3.4.15. SSTS—SECONDARY PCI-PCI STATUS REGISTER (DEVICE 1)
Address Offset:
Default Value:
Access:
1E–1Fh
02A0h
Read Only, Read/Write Clear
SSTS is a 16-bit status register that reports the occurrence of error conditions associated with the secondary
side (i.e., A.G.P. side) of the “virtual” PCI-to-PCI bridge in PAC.
Bit
Description
15 Detected Parity Error (DPE1)—R/WC.
1=Indicates PAC’s detection of a parity error in either the data or address phase. Software
resets this bit to 0 by writing a 1 to it. Note that the function of this bit is not affected by the
PERRE1 bit.
14 Received System Error (SSE1)—R/WC.
1=PAC detects GSERR# assertion on A.G.P. Software resets this bit to 0 by writing a 1 to it.
13 Received Master Abort Status (RMAS1)—R/WC.
1=PAC terminated a Host-to-A.G.P. with an unexpected master abort. Software resets this bit
to 0 by writing a 1 to it.
12 Received Target Abort Status (RTAS1)—R/WC.
1=PAC-initiated transaction on A.G.P. is terminated with a target abort. Software resets RTAS1
to 0 by writing a 1 to it.
11:9 Reserved.
8 Data Parity Detected (DPD1)—R/WC. This bit is set to a 1, when all of the following conditions
are met. Software resets this bit to 0 by writing a 1 to it.
1. PAC asserted GPERR# or sampled GPERR# asserted.
2. PAC was the initiator for the operation in which the error occurred.
3. The SPERRE bit in the BCTRL register is set to 1.
7:0 Reserved.
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