82443LX Datasheet, PDF (51/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

E
INTEL 82443LX (PAC)
3.3.20. DRAMXC—DRAM EXTENDED CONTROL REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
6A–6Bh
0000h
Read/Write
Bit
Description
15:8 Reserved.
7:5 SDRAM MODE SELECT
Bits[7:5] Operating Mode
000
Normal Operating Mode (default)
001
NOP Command Enabled (NOPCE). This overrides the output values of SRAS#,
SCAS#, and WE# to be 1 1 1 (i.e., a NOP command). When in this mode, the only
SDRAM operation that PAC will perform is a NOP command.
010
All Banks Pre-charge Command Enable (ABPCE). This overrides the output values
of SRAS#, SCAS#, and WE# to be 0 1 0 (i.e., Pre-charge command). When in this
mode the only SDRAM operation that PAC will perform is a Pre-charge command.
011
Mode Register Set Command Enable (MRSCE). This overrides the output values of
SRAS#, SCAS#, and WE# to be 0 0 0 (i.e., MRS command). When in this mode the
only SDRAM operation that PAC will perform is a MRS command.
100
CBR Cycle Enable (CBRC). This overrides the output values of SRAS#, SCAS#, and
WE# to be 0 0 1 (i.e., Refresh command). When in this mode the only SDRAM
operation that PAC will perform is a Refresh command.
101–11X Reserved.
4 Reserved.
3:2 Page Timeout Select (PTOS). Clock Counts are elapsed time waiting for a new Request in the
REQW State.
00=16 Clocks (default)
01=Reserved
10=Reserved
11=Reserved
1:0 Close Both Banks Control (CBBC)
00=Close Both Banks on Arb Switch PageMiss (default)
01=Reserved
10=Reserved
11=Reserved
51