82443LX Datasheet, PDF (34/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Address
Offset
A8–ABh
B0–B3h
B4h
B8–BBh
BCh
BDh
Table 8. PCI Configuration Space—Device 0 (Host-to-PCI Bridge)
Register
Symbol
Register Name
Power Down Access
Default Value

A.G.P. Command Register
AGPCTRL A.G.P. Control Register
00000000h
R/W
00000000h
R/W
APSIZE Aperture Size Control Register
0000h
R/W
ATTBASE Aperture Translation Table Base Register 00000000h
R/W
AMTT A.G.P. MTT Control Register
00h
R/W
LPTT A.G.P. Low Priority Transaction Timer Reg.
00h
R/W
Page #
62
63
64
65
65
65
Address
Offset
00−01h
02−03h
04−05h
06−07h
08
0Ah
0Bh
0Eh
18h
19h
1Ah
1Bh
1Ch
1Dh
1E−1Fh
20−21h
22−23h
24−25h
26−27h
3E−3Fh
Table 9. PCI Configuration Space—Device 1 (“Virtual” PCI-to-PCI Bridge)
Register
Symbol
Register Name
Power Down Access
Default Value
VID1
DID1
PCICMD1
Vendor Identification
Device Identification
PCI Command Register
8086h
RO
7181h
RO
0000h
R/W
PCISTS1 PCI Status Register
RID1 Revision Identification
02A0h
00h
RO,
R/WC
RO
SUBC1
BCC1
HDR1
Sub-Class Code
Base Class Code
Header Type
04h
RO
06h
RO
01h
RO
PBUSN
SBUSN
SUBUSN
Primary Bus Number Register
Secondary Bus Number
Subordinate Bus Number
00h
RO
00h
R/W
00h
R/W
SMLT
IOBASE
IOLIMIT
Secondary Bus Master Latency Timer
I/O Base Address Register
I/O Limit Address Register
00h
R/W
F0h
R/W
00h
R/W
SSTS
MBASE
MLIMIT
Secondary Status Register
Memory Base Address Register
Memory Limit Address Register
02A0h
R/W
FFF0h
R/W
0000h
R/W
PMBASE Prefetchable Memory Base Address Reg.
FFF0h
R/W
PMLIMIT Prefetchable Memory Limit Address Reg.
0000h
R/W
BCTRL Bridge Control Register
0000h
R/W
Page #
66
66
66
67
67
67
68
68
68
69
69
69
70
70
71
72
72
73
73
74
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