82443LX Datasheet, PDF (77/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

E
INTEL 82443LX (PAC)
Extended
Pentium^® II
Processor
Memory
64 GB
4 GB
Extended
EISA
Memory
1 GB (TOM)
Extended
ISA
Memory
DOS
Compatibility
Memory
Optional Fixed
Memory Hole
(1 MB)
16 MB
15 MB
1 MB
640 KB
512 KB
o KB
0FFFFFh
1 MB
DOS
Compatibility
Memory
0F0000h
0EFFFFh
0E0000h
0DFFFFh
0C0000h
0BFFFFh
0A0000h
09FFFFh
080000h
07FFFFh
000000h
Upper BIOS Area
(64 KB)
Lower BIOS Area
(64 KB)
16KBx4
Expansion Card
BIOS and Buffer
Area (128 KB)
16KBx8
Standard PCI/ISA
Video Memory
(SMM Mem)
128 KB
Optional Fixed
Memory Hole
DOS Area
(512 KB)
960 KB
896 KB
768 KB
640 KB
512 KB
0 KB
MEM_ADD
Figure 4. Detailed Memory System Address Map
Video Buffer Area (A0000h−BFFFFh)
The 128-KB graphics adapter memory region is normally mapped to a legacy video device on the PCI bus
(typically VGA controller). This area is not controlled by attribute bits and CPU-initiated cycles in this region
are forwarded to the PCI bus or A.G.P. for termination. This region is also the default region for SMM space.
The BCTRL (PCI-PCI Bridge Control Register) configuration registers of “virtual” PCI-to-PCI Bridge controls
whether these accesses will be forwarded to PCI or to A.G.P. This applies to accesses initiated from any of
the system interfaces (i.e., CPU bus, PCI or A.G.P.). Note that for A.G.P.<->PCI accesses, only write
operations from PCI to A.G.P. are supported (i.e., A.G.P. -> PCI writes are not supported; PCI<->AGP reads
are not supported). For more details see the PCI-to-PCI Bridge Control register description.
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