82443LX Datasheet, PDF (54/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Bit
Description
5:4 RCSA[5]# & RCSB[5]#/MAB[11] Buffer Strength. This field sets the buffer strength for
RCSA[5]# & RCSB[5]#/MAB[11] pins.
00=48 mA
01=42 mA
10=22 mA
11=Reserved
3:2 RCSA[6]#/MAB[2] & RCSB[6]#/MAB[12] Buffer Strength. This field sets the buffer strength for
RCSA[6]#/MAB[2] & RCSB[6]#/MAB[12] pins.
00=48 mA
01=42 mA
10=22 mA
11=Reserved
1:0 RCSA[7]#/MAB[3] & RCSB[7]#/MAB[13] Buffer Strength. This field sets the buffer strength for
RCSA[7]#/MAB[3] & RCSB[7]#/MAB[13] pins.
00=48 mA
01=42 mA
10=22 mA
11=Reserved
NOTES:
WE#[3:0], SRAS#[3]/MAB[5], SCAS#[3]/MAB[4], SRAS#[2:0] and SCAS#[2:0] are no longer programmable.
Their strength will be hard-wired to 42 mA (medium strength).
3.3.22. MTT—MULTI-TRANSACTION TIMER REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
70h
00h
Read/Write
MTT is an 8-bit register that controls the amount of time that PAC’s arbiter allows a PCI initiator to perform
multiple back-to-back transactions on the PCI bus. PAC’s MTT mechanism is used to guarantee the fair
share of the PCI bandwidth to an initiator that performs multiple back-to-back transactions to fragmented
memory ranges (and as a consequence it can not use long burst transfers).
Bit
Description
7:3 Multi-Transaction Timer Count Value. The number of clocks programmed in this field
represents the guaranteed time slice (measured in PCI clocks) allotted to the current agent, after
which PAC will grant the bus as soon as other PCI initiators request the bus. The default value of
MTT is 00h and disables this function. The MTT value can be programmed with 8 clock
granularity in the same manner as the MLT register. For example, if the MTT is programmed to
18h, then the selected value corresponds to the time period of 24 PCI clocks.
2:0 Reserved.
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