82443LX Datasheet, PDF (124/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Table 31. AC Timing Measurement Points
Clock
V_test
V_step
Notes
CPU interface
HCLK (2.5V)
1.25V
1.0V for GTL+ signal group
1.25V for CMOS, APIC signals
DRAM interface
1.25V
1.4V for SDRAM
1
HCLK (2.5V)
1.5V for EDO
PCI interface
1.5V
n/a
2
PCICLK(3.3V)
AGP device
0.4Vcc
0.4Vcc
3
HCLK (2.5)
NOTES:
1. DRAM interface AC timing measurement is relative to 2.5V of HCLK, since the HCLK input to PAC is a
2.5V signal. The DRAM AC timing in Table 24 and Table 25 are valid for both SDRAM and EDO.
2. Although the PCICLK is a 3.3V clock, the PCI interface of PAC operates in a 5V PCI environment. Via
PCI 2.1 spec, the V_test is1.5V.
3. Although the HCLK input of PAC is a 2.5V clock, the AGP interface of PAC operates in a 3.3V
environment.
5.7. DRAM TIMING RELATIONSHIPS WITH REGISTER SETTINGS
This section shows the DRAM timing relationship with respect to bit settings in the DRAM Timing (DRAMT)
register (address offset 58h). The values in this register affect both leadoff and burst timings. The CPU to
DRAM memory read performance summary for EDO and SDRAM are shown in Table 32 and Table 33.
NOTE
1. PH is page hit.
2. RM is row miss.
3. PM is page miss.
4. The leadoff clock counts of a back-to-back burst cycle is also shown as a pipeline leadoff
5. All leadoff counts will add one more clock when ECC is enabled.
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