82443LX Datasheet, PDF (86/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
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To create a memory array certain rules must be followed. The following set of rules allows for optimum
configurations.
Rules for populating a PAC Memory Array
• DIMM sockets can be populated in any order. However, to take advantage of potentially faster MA timing
it is recommended to populate sockets in order.
• SDRAM and EDO DIMMs can be mixed within the memory array.
• The DRAM Timing register, which provides the DRAM speed grade control for the entire memory array,
must be programmed to use the timings of the slowest DRAMs installed.
PAC Memory Array Configurations
PAC offers multiplexed memory interface signals to support both large memory arrays (to reach a maximum
memory size of 1 GB (EDO) or 512 MB (SDRAM), or smaller memory arrays (with minimal external signal
buffering). PAC offers two memory configuration types, each offering a different memory signal interface.
These memory configurations are selectable upon Boot/RESET by a strapping option on the CKE signal
(please refer to the CKE signal description table for more details).
Configuration #1: Enables large memory arrays (up to 8 rows) with two copies of Row Address Strobe/Chip
Selects (RCSAxx# & RCSBxx#), and extra copies of Column Address Strobe/Data Mask 5 & 1, (CDQB[5 &
1]# are the most loaded CAS#/DQM signals when using ECC DIMMs). Four SRAS#, SCAS# and WE#
signals are also provided. This configuration supports Single-Sided and Double-Sided x8 and x16 DIMMs,
and Single-Sided x4 DIMMs. The Configuration #1 interface signals are shown in Figure 5.
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