82443LX Datasheet, PDF (115/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
Table 24. DRAM INTERFACE TIMING, 66 MHz (Configuration #1)
Functional Operating Range (VTT = 1.5V ± 10%, Vcc = 3.3V ±5%; TCASE = 0oC to +100oC)
Symbol
Parameter
Min
Max Units Figure Notes
t10 WE# Valid Delay from HCLKIN Rising
1.5
7.0
ns
17
0 pF
t11 MAA[13:2]#, MAB[1:0]# Valid Delay from
1.5
7.0
ns
HCLKIN Rising, SDRAM Read/Write cycles
17
0 pF
t12 SRAS[2:0]#, SRAS[3]#/MAB[5] Valid Delay
1.5
7.0
ns
from HCLKIN Rising
17
0 pF
t13 SCAS[2:0]#, SCAS[3]#/MAB[4] Valid Delay
1.5
7.0
ns
from HCLKIN Rising
17
0 pF
t14 RCSA[5:0]#, RCSA[7:6]#/MAB[3:2],
RCSB[7:0]#/MAB[13:6] Valid Delay from
HCLKIN Rising
1.5
7.0
ns
17
0 pF
t15 CDQA[7:0]#, CDQB[1]#, CDQB[5]# Valid
Delay from HCLKIN Rising
1.5
6.5
ns
17
0 pF
t16 MD[63:0], MECC[7:0] Valid Delay from
HCLKIN Rising
1.0
6.0
ns
17
0 pF
t17 MD[63:0], MECC[7:0] Setup Time to HCLKIN 1.0
Rising
ns
18
note1
t18 MD[63:0], MECC[7:0] Hold Time from
2.0
HCLKIN Rising
ns
18
note1
t19 CKE Valid Delay from HCLKIN Rising
1.5
7.0
ns
17
0 pF
115