82443LX Datasheet, PDF (97/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

E
INTEL 82443LX (PAC)
4.3.6.1.
Enabling Single Clock Command Mode
MA Wait State(MAWS). This bit selects FAST or SLOW MA bus timing. Note that SLOW timing is equal to
FAST + 1 in terms of clock numbers for EDO. For SDRAM, FAST timing means zero MA wait state. This
setting will enable the PAC(440LX) to support single clock command mode; SLOW means one MA wait state,
which forces the PAC to support the normal operation only (one command per two clocks).
4.3.6.2.
Restrictions For Supporting Single Clock Command Mode
There is no support of single clock command mode for the configuration #1(4 DIMM design) because of the
external buffer delay (not able to meet the AC timing). To support single clock command mode in
configuration #2, the memory controller of 440LX needs to toggle memory address (CAS assertions) on every
clock edge. This tightens memory AC timing requirements on the address signals. Because the loading of
SDRAM modules has the direct effect on the AC timing, the maximum loading of memory module is limited
while supporting single clock command mode. The following table shows the population rules and types (x8,
x16, x32) of DIMM module that can be supported for running single clock command mode.
Table 18. Restrictions For Single Clock Command Mode Support
Memory config #2 (3DIMMs)
Types of SDRAM module
MAB MAA MAA
DIMM #3 #2 #1
Row# 5/4 3/2 1/0
SS/DS x8
DS x16
ECC & nonECC
SS x16
ECC & nonECC
x
no
yes
x
no
yes
x
no
yes
xx
no
yes
x
x
no
yes
xx
no
no
xx
x
no
no
NOTES:
x means populated, SS means single-sided, DS means double-sided.
4.3.6.3.
Conclusion For Single Clock Command Mode Support
There is no support of single clock command mode for configuration #1(4 DIMMs solution). For a 3 DIMM
design, as shown in the above table, set the MAWS bit to 1 to support SDRAM single clock command mode
when DIMM sockets on the MAA copy is populated with:
• maximum 1 row of (0,1,2,3), and/or maximum 1 row of (4,5) for x16, regardless of ECC or non-ECC
SDRAM
4.3.7. SUPPORT FOR 2 AND 4 BANKS SDRAM
The PAC supports both 2 and 4-bank SDRAM components. However, regardless of populating either 2 or 4-
bank SDRAM DIMMs in a 440LX system, the SDRAM interface of the PAC can only open 2 pages at any
time. The PAC is not able to open 4 pages simultaneously, even a 4-bank SDRAM module is used.
97