82443LX Datasheet, PDF (46/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
3.3.17. PAM—PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0]) (DEVICE 0)
Address Offset:
Default Value:
Attribute:
59 (PAM0)−5Fh (PAM6)
00h
Read/Write
PAC allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 640-KB
to 1-MB address range. Seven Programmable Attribute Map (PAM) Registers are used to support these
features. Cacheability of these areas is controlled via the MTRR registers in the Pentium II processor. Two
bits are used to specify memory attributes for each memory segment. These bits apply to both host accesses
and PCI/A.G.P. initiator accesses to the PAM areas. These attributes are:
RE Read Enable. When RE=1, the host/A.G.P. read accesses to the corresponding memory segment
are claimed by PAC and directed to main memory. Conversely, when RE=0, the read access is
directed to PCI.
WE Write Enable. When WE=1, the host/A.G.P. write accesses to the corresponding memory segment
are claimed by PAC and directed to main memory. Conversely, when WE=0, the write access is
directed to PCI.
The RE and WE attributes permit a memory segment to be read only, write only, read/write, or disabled (i.e.,
if a memory segment has RE=1 and WE=0, the segment is read only). Each PAM Register controls two
regions, typically 16 KB. Each of these regions has a 4-bit field. The 4 bits that control each region have the
same encoding and are defined in Table 10.
Table 10. Attribute Bit Assignment
Bits [7, 3] Bits [6, 2] Bits [5, 1] Bits [4, 0]
Reserved Reserved
WE
RE
Description
X
X
0
0
Disabled. DRAM is disabled and all accesses are
directed to PCI. PAC does not respond as a PCI
target for any read or write access to this area.
X
X
0
1
Read Only. Reads are forwarded to DRAM and
writes are forwarded to PCI for termination. This
write protects the corresponding memory segment.
PAC will respond as a PCI target for read accesses
but not for any write accesses.
X
X
1
0
Write Only. Writes are forwarded to DRAM and
reads are forwarded to the PCI for termination. PAC
will respond as a PCI target for write accesses but
not for any read accesses.
X
X
1
1
Read/Write. This is the normal operating mode of
main memory. Both read and write cycles from the
host are claimed by PAC and forwarded to DRAM.
PAC will respond as a PCI target for both read and
write accesses.
As an example, consider a BIOS that is implemented on the expansion bus. During the initialization process,
BIOS can be shadowed in main memory to increase the system performance. When a BIOS is copied in
main memory, it should be copied to the same address location. To shadow BIOS, the attributes for that
address range should be set to write only. BIOS is shadowed by first doing a read of that address. This read
is forwarded to the expansion bus. The host then does a write of the same address, which is directed to main
memory. After BIOS is shadowed, the attributes for that memory area are set to read only so that all writes
are forwarded to the expansion bus.
46