82443LX Datasheet, PDF (66/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
3.4. A.G.P. Configuration Registers—(Device 1)
3.4.1. VID1—VENDOR IDENTIFICATION REGISTER (DEVICE 1)
Address Offset:
Default Value:
Attribute:
00–01h
8086h
Read Only
The VID1 register contains the vendor identification number for function 1. This 16-bit register combined with
the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect.
Bit
Description
15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID=8086h.
3.4.2. DID1—DEVICE IDENTIFICATION REGISTER (DEVICE 1)
Address Offset:
Default Value:
Attribute:
02–03h
7181h
Read Only
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes
to this register have no effect.
Bit
Description
15:0 Device Identification Number. This is a 16-bit value assigned to PAC Device 1. PAC Device 1
DID=7181h.
3.4.3. PCICMD1—PCI-PCI COMMAND REGISTER (DEVICE 1)
Address Offset:
Default:
Access:
04–05h
0000h
Read/Write
This 16-bit register provides basic control over the “virtual” PCI-to-PCI bridge entity embedded within PAC. In
this way, PAC’s A.G.P. interface is handled by the standard control mechanism of the PCI-to-PCI bridge,
where A.G.P. corresponds to the Secondary Bus of the bridge.
Bit
Description
15:9 Reserved.
8 SERR# Enable (SERRE1).
1=Enable. PAC’s common SERR# signal driver (common for Primary PCI and A.G.P.) is
enabled for the error conditions that occurred on the A.G.P. (including GSERR# assertion
and parity errors), and SERR# is asserted for all relevant bits set in the PCISTS1. If both
SERRE and SERRE1 are reset to 0, then SERR# is never driven by PAC. Also, if this bit is
set and the Parity Error Response Enable Bit (Register 3Eh, Device #1, Bit 0) is set, then
PAC will report ADDRESS parity errors on A.G.P. (when it is potential target).
0=Disable.
7:0 Reserved.
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