82443LX Datasheet, PDF (80/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
NOTE
When programming the APSIZE register such that the APBASE register bits change from “read only”
(forced to 0) to “read/write,” the value of those bits is undefined and must be written first to have a
known value. Note that the Aperture Size register (Offset B4h, Device 0) programming only effects the
accessibility of bits 27:22 in the Aperture Base Register (Offset 10–13h, Device 0).
Accesses within the aperture range are forwarded to main memory. PAC translates the originally issued
addresses via a translation table that is maintained in main memory. The aperture range should be
programmed as not cacheable in the processor caches.
NOTE
The plug-and-play software configuration model does not allow overlap of different address ranges.
Therefore, the A.G.P. aperture and the A.G.P. Memory Range are independent address ranges that
may be contiguous, but not overlapping.
4.1.1.4.
Address Mapping of PCI Devices on A.G.P.
The A.G.P. Memory Range registers are used also to allocate a memory address range for the PCI device
(i.e., 66-MHz/3.3V PCI agent attached to the A.G.P. port). The same applies in the case of a multi-functional
A.G.P. device where one or multiple of the functions are implemented as PCI-only devices.
4.1.2. SYSTEM MANAGEMENT MODE (SMM) MEMORY RANGE
PAC supports the use of main memory as SMM memory when the system management mode is enabled.
When this function is disabled, the memory address range A0000h−BFFFFh is normally defined as a video
buffer range where accesses are directed to either A.G.P. or PCI and physical DRAM memory is not
accessed. When SMM is enabled via SMRAM configuration register the A0000h−BFFFFh range is used as a
SMM RAM and no accesses from PCI or A.G.P. bus are allowed. CPU bus cycles executed in SMM mode
access the A0000h−BFFFFh range by being mapped to a corresponding physical DRAM address range
instead of being forwarded. Before this space is accessed in SMM mode, the corresponding main memory
range must be first initialized. This is done using SMRAM register. Opening of SMM space in the 0C0000h−
0CFFFFh is also allowed using the SMRAM register.
NOTE
A PCI or A.G.P. initiator can not access SMM space.
4.1.3. MEMORY SHADOWING
Any block of memory that can be designated as read only or write only can be “shadowed” in main memory.
Typically, this is done to allow ROM code to execute more rapidly out of main memory. ROM is used as a
read only during the copy process while DRAM is designated write only at the same time. After copying, the
DRAM is designated read only so that ROM is shadowed. CPU bus transactions are routed accordingly.
4.1.4. I/O ADDRESS SPACE
PAC does not support the existence of any other I/O devices besides itself on the host bus. PAC generates
either PCI or A.G.P. bus cycles for all CPU I/O accesses. PAC contains two internal registers in the CPU I/O
space—CONFADD register and CONFDATA register. These locations are used to implement PCI
configuration space access mechanism and is described in the Register Description section.
The CPU allows 64 KB to be addressed within the I/O space. PAC propagates the CPU I/O address without
any translation on to the destination bus and, therefore, provides addressability for 64-KB locations. Note that
the upper three locations past the 64-K boundary can be accessed only during I/O address wrap-around
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