82443LX Datasheet, PDF (108/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
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4.8.6. SOFT RESET
A soft reset is defined as only resetting the CPU (no other devices in the system are reset). There are five
sources of soft reset in the system:
• CPU shutdown bus cycle
• I/O write to the PAC Reset Control Register (offset 93h)
• I/O write to the keyboard controller
• I/O write to the PIIX4 port 92h
• I/O write to the PIIX4 Reset Control Register (I/O address CF9h)
When PAC detects a CPU shutdown bus cycle, it terminates the Host bus cycle with a TDRY#, with a no data
response type as defined in the Pentium II processor datasheet. PAC then asserts the INIT# output for a
minimum of 4 host clocks.
PAC can be programmed to generate a soft reset through the Reset Control Register (configuration offset
93h). PAC asserts INIT# for a minimum of 4 host clocks if bit 3=0, bit 1=1 and bit 2 is written from a 0 to a 1.
A soft reset from the keyboard controller will be signaled into the PIIX4 through the RCIN# signal on the PIIX4
The PIIX4 will then generate the INIT signal active. A write to I/O port 92h, bit 0, also causes PIIX4 to assert
INIT. A write to the PIIX4 Reset Control Register also causes PIIX4 to assert INIT.
The system combines PAC INIT# output with the PIIX4 INIT output as shown above to generate the INIT#
signal for the CPU(s).
4.8.7. CPU BIST
PAC can be programmed to activate BIST mode of the CPU through the Reset Control Register
(configuration offset 93h). If PAC activates the CPU’s BIST function, a hard reset must then be initiated (after
BIST completion). The BIST mode sets the IOQ depth of the processor and PAC to 1. This is not a valid
operating condition for PAC.
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