82443LX Datasheet, PDF (73/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
3.4.18. PMBASE—PREFETCHABLE MEMORY BASE ADDRESS REGISTER (DEVICE 1)
Address Offset:
Default Value:
Access:
24–25h
FFF0h
Read/Write
This register controls the CPU to A.G.P. prefetchable memory accesses routing based on the following
formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
This register must be initialized by the configuration software. For address decode, address bits A[19:0] are
assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1-MB boundary.
Bit
Description
15:4 Memory Address Base. Bits [15:4] corresponds to A[31:20] of the 32-bit memory address.
Default=FFFh
3:0 Reserved. Read as 0s.
3.4.19. PMLIMIT—PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER (DEVICE 1)
Address Offset:
Default Value:
Access:
26–27h
0000h
Read/Write
This register controls the CPU to A.G.P. prefetchable memory accesses routing based on the following
formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
This register must be initialized by the configuration software. For address decode, address bits A[19:0] are
assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB
aligned memory block.
Bit
Description
15:4 Memory Address Limit. Corresponds to A[31:20] of the 32-bit memory address. Default=000h
3:0 Reserved. Read as 0s.
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