82443LX Datasheet, PDF (32/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
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asserts AD12 and then claims the cycle itself. To access PCI Device #2 PAC asserts AD13, for PCI Device
#3 PAC asserts AD14, and so forth up to PCI Device #20 for which PAC asserts AD31 for PCI Type 0
Configuration Cycles. Only one AD line is asserted at a time. All device numbers higher than 20 cause a type
0 configuration access with no IDSEL asserted, which results in a master abort. To access A.G.P. Device #0
PAC will assert GAD16, to access A.G.P. Device #1 PAC will assert GAD17, for A.G.P. Device #2 PAC will
assert GAD18, and so forth up to Device #15 for which will assert GAD31. Only one GAD line is asserted at a
time. All device numbers higher than 15 cause a Type 0 A.G.P. configuration access with no IDSEL asserted,
which result in a Master Abort.
Type 1 Access: If the CONFADD[BUSNUM]≠0 but NOT within the range defined as:
SUBORDINATE-BUS-NUMBER ≥ range ≥ SECONDARY-BUS-NUMBER,
then a Type 1 Configuration cycle is performed on the Primary PCI bus (i.e., BUS #0). Note that
SECONDARY-BUS-NUMBER and SUBORDINATE-BUS-NUMBER are values contained within the
corresponding configuration registers of PAC’s “virtual” PCI-to-PCI Bridge entity. CONFADD[23:2] are
mapped directly to AD[23:2]. AD[1:0] are driven to 01 to indicate a Type 1 Configuration cycle. All other lines
are driven to 0.
3.1.3.3.
Mapping of Configuration Cycles on A.G.P.
From the AGPset configuration perspective, A.G.P. is another PCI bus interface residing on a Secondary Bus
side of the “virtual” PCI-to-PCI Bridge embedded within PAC. On the Primary Bus side the “virtual” PCI-to-PCI
bridge is attached to the BUS #0. Therefore the Secondary side would be denoted as a BUS#1 in the system
where configuration software would scan devices on the PCI bus #0 going from the lowest (0) to the highest
(20) device number. The “virtual” PCI-to-PCI bridge entity is used to map Type #1 PCI Bus Configuration
cycles directed to BUS #0 onto the Type #0 or Type #1 configuration cycles on the A.G.P. interface based on
the following rule:
If the CONFADD[BUSNUM]≠0 but within the range defined as:
SUBORDINATE-BUS-NUMBER ≥ range ≥ SECONDARY-BUS-NUMBER
then Type 0 or Type 1 Configuration cycles are performed on A.G.P. If the Bus Number matches a
SECONDARY-BUS-NUMBER of the “virtual” PCI-TO-PCI device, then Type 0 configuration cycles are
executed on the A.G.P. Otherwise, Type 1 cycles are performed on A.G.P.
To prepare for mapping of the configuration cycles on A.G.P., the initialization software will go through the
following sequence:
1. Scan all devices residing at the Primary PCI bus (i.e., bus #0) using Type 0 configuration accesses.
2. For every device residing at bus #0 which implements PCI-to-PCI bridge functionality, it will configure the
secondary bus of the bridge with the appropriate number and scan further down the hierarchy. (This
process will include the configuration of the “virtual” PCI-TO-PCI Bridge within PAC used to map the
A.G.P. address space in a software standard manner.)
3.2. PCI Configuration Space (Device 0 and Device 1)
PAC is implemented as a dual PCI device residing within a single physical component:
• Device 0=Host Bridge (includes PCI bus #0 interface, Main Memory Controller, Graphics Aperture
control, PAC’s specific A.G.P. control registers).
• Device 1=“Virtual” PCI-to-PCI Bridge (includes mapping of A.G.P. space and standard PCI interface
control functions of the PCI-to-PCI Bridge).
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