82443LX Datasheet, PDF (106/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
4.8.3. SYSTEM RESET
There are two types of system reset. A “hard” reset causes the entire system to reset and is initiated by the
PIIX4. A hard reset can be initiated by either PWROK being asserted (from the power supply/reset button) or
by writing to the PIIX4 (I/O address CF9h). A “soft” reset only resets the CPU.
A soft reset can be initiated by either PAC or the PIIX4. There are several ways to initiate a soft reset. PIIX4
can initiate a soft reset via a write to the PIIX4 Reset Control Register or an I/O write to port 92h. Additionally,
the PIIX4 initiates a soft reset when RCIN# is asserted from the keyboard controller. PAC initiates a soft
reset when the RCPU bit is written. Both the PIIX4 and PAC initiate soft reset via the INIT signal to the
processor. Thus, the INIT signal from the PIIX4 should be tied to the INIT signal from PAC and routed to the
CPU(s).
4.8.4. PAC RESET STRUCTURE
The system reset structure is shown in Figure 13.
4.8.5. HARD RESET
Hard Reset is defined as a reset where all the components in the entire system are reset. There are two
sources of hard reset in the system:
• During Power-up, PWROK asserted (typically by the power supply) 1 ms after the system power has
stabilized.
• I/O write to the PIIX4 Reset Control register (I/O address CF9h).
PIIX4 generates a hard reset for the system when the PWROK signal is sampled inactive (low). PIIX4
generates PCIRST# for both the A.G.P. and PCI bus. PAC uses the PCIRST# input connected to the RSTIN#
pin to generate CPURST# (for the Pentium II processor(s)), and CRESET# (to the frequency control logic and
I/OAPIC). PAC asserts CPURST# and CRESET# when RSTIN# is sampled low, and continues assert
CPURST# for 1 msec, and CRESET# for 1 msec plus 2 HCLKINs, after the rising edge of the RSTIN# signal.
The assertion of CPURST# must be synchronous to the HCLKIN.
PIIX4 can be programmed to generate a hard reset through the Reset Control register (I/O Address CF9h).
PIIX4 drives PCIRST# low for 1 msec and the reset continues as described above.
PAC configuration straps on the ECCERR#, MECC[0] and CKE pins are sampled on the rising edge of
RSTIN#.
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