82443LX Datasheet, PDF (20/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Signal
CKE
Table 2. DRAM Interface Signals
Type
Description
I/O
LVTTL
Clock Enable (SDRAM): This signal is used to enable/disable the SDRAM clock
(internally within the SDRAM component). When “high,” it enables normal SDRAM
operation. When “low,” it deactivates the SDRAM clock and the SDRAM
components enter Power Down Mode. Note that all SDRAM banks must be
pre-charged before CKE is negated.
The SDRAM Power Down Mode is used only for the PAC DRAM array power
management.
The CKE signal must be externally buffered, using a CMOS buffer, if SDRAM
power management capability is utilized.
Note that starting with the assertion of RSTIN#, and until 4 clocks of the
CPURST# signal negation, this signal will be controlled as an input to allow
sampling of the strap attached to this pin. CKE is connected to a 20 kΩ internal
pull-down resistor.
2.1.3. PCI INTERFACE SIGNALS
Name
AD[31:0]
DEVSEL#
FRAME#
IRDY#
Table 3. PCI Interface Signals
Type
Description
Standard PCI Signals
I/O PCI PCI Address/Data: These signals are connected to the PCI address/data bus.
Address is driven with FRAME# assertion and data is driven or received on
following clocks.
I/O PCI Device Select: Assertion indicates that a PCI target device has decoded its
address as the target of the current access. PAC asserts DEVSEL# if the current
access is:
• within Main Memory
• within the A.G.P. aperture
• resides on the A.G.P. interface
• a configuration cycle targeting the PAC
As an input, this signal indicates whether a device on the bus has been selected.
I/O PCI Frame: Assertion indicates the address phase of a PCI transfer. Negation indicates
that one more data transfer is desired by the cycle initiator.
I/O PCI Initiator Ready: Asserted when the initiator is ready for a data transfer.
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