82443LX Datasheet, PDF (40/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Bit
Description
31:28 Upper Programmable Base Address bits (R/W). These bits (default=0) locate the range size
which is selected by the lower bits (that are either hardwired to 0 or behave as hardwired to 0
depending on the contents of the APSIZE register).
27:22 Lower “Hardwired”/Programmable Base Address bits. These bits behave as a hardwired or
as a programmable depending on the contents of the APSIZE register as defined below:
27
26
25
24
23
22
Aperture Size
R/W R/W
R/W R/W
R/W R/W
R/W R/W
R/W R/W
R/W 0
0
0
R/W
R/W
R/W
R/W
0
0
0
R/W
R/W
R/W
0
0
0
0
R/W
R/W
0
0
0
0
0
R/W
0
0
0
0
0
0
4 MB
8 MB
16 MB
32 MB
64 MB
128 MB
256 MB
Bits [27:22] are controlled by bits [5:0] of the APSIZE register. For example, if bit APSIZE[5]=0,
APBASE[27]=0. If APSIZE[5]=1, APBASE[27]=R/W. The same applies, correspondingly, to other
bits. The default for APSIZE[5:0] (000000b) forces the APBASE[27:22] default to be 000000b
(i.e., all bits respond as hardwired to 0).
NOTE
When programming the APSIZE register such that APBASE register bits change from “read
only” to “read/write,” the value of those bits is undefined and must be written first to have a
known value.
21:0 Reserved.
3.3.11. CAPPTR—CAPABILITIES POINTER (DEVICE 0)
Offset:
Default:
Access:
34h
A0h
Read Only
The CAPPTR provides the offset that is the pointer to the location where A.G.P. standard registers are
located.
Bit
Description
7:0 Pointer to the start of A.G.P. standard register block. Default Value=A0h
40