82443LX Datasheet, PDF (37/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
3.3.4. PCISTS—PCI STATUS REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
Size:
06–07h
0290h
Read Only, Read/Write Clear
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI master abort and PCI target abort on
the PCI bus. PCISTS also indicates the DEVSEL# timing that has been set by PAC hardware for target
responses on the PCI bus. Bits [15:12] and bit 8 are read/write clear and bits [10:9] are read only.
Bit
Description
15 Detected Parity Error (DPE)—R/WC. Software sets DPE to 0 by writing a 1 to this bit.
1 = Indicates PAC’s detection of a parity error in either the data or address phase of the Primary
PCI bus transactions. Note that the function of this bit is not affected by the PERRE bit.
14 Signaled System Error (SSE)—R/WC. Software sets SSE to 0 by writing a 1 to this bit.
1 =When PAC PCI interface logic asserts the SERR# signal, this bit is set to a 1.
13 Received Master Abort Status (RMAS)—R/WC. Software resets this bit to 0 by writing a 1 to it.
1 = When PAC terminates a PCI bus transaction (PAC is a PCI master) with an unexpected
master abort, this bit is set to a 1. Note that master abort is the normal and expected
termination of PCI special cycles.
12 Received Target Abort Status (RTAS)—R/WC. Software resets RTAS to 0 by writing a 1 to it.
1 = When a PAC-initiated PCI transaction is terminated with a target abort, RTAS is set to 1.
PAC also asserts SERR# if enabled in the ERRCMD register.
11 Reserved.
10:9 DEVSEL# Timing (DEVT)—RO. This 2-bit field indicates the timing of the DEVSEL# signal when
PAC responds as a target on the PCI Bus.
01b=Medium (Hardwired). Indicates the time when a valid DEVSEL# can be sampled
by the initiator of the PCI cycle.
8 Data Parity Detected (DPD)—R/WC. Software sets DPD to 0 by writing a 1 to this bit.
1 = This bit is set to a 1, when all of the following conditions are met:
1. PAC asserted PERR# or sampled PERR# on the PCI Bus.
2. PAC was the initiator for the operation in which the error occurred on the PCI bus.
3. The PERRE bit in the Primary PCI Command register is set to 1.
7:0 Reserved.
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