TDA5240 Datasheet, PDF (96/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
Reset
Bit:SLRXEN == 1
Bit:MSEL == 0
Bit:SLRXEN == 0
Bit:MSEL == 0
Sleep Mode
Chip is idle
Init
Initialize RX-Part
Bit:SLRXEN == 0
or
Bit:MSEL == 1
Bit:SLRXEN == 1
Bit:MSEL == 0
Run Mode
Slave
Bit:SLRXEN == 0
or
Bit:MSEL == 1
Chip is permanently
active
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == 1
Bit:MSEL == 0
Bit:SLRXEN == X
Bit:MSEL == 0
Init
Initialize RX-Part
Bit:SLRXEN == X
Bit:MSEL == 0
Bit:SLRXEN == X
Bit:MSEL == 0
ToTim Timeout == X
Bit:SLRXEN == X
Bit:MSEL == 1
EOM2SPM == 1
Bit:SLRXEN == X
Bit:MSEL == 1
Self Polling
Mode
Chip is periodically active
and searching for
WU criteria
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 1
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 0
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 1
Run Mode
Self Polling
Chip is permanently
active
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 0
Figure 68 Global State Diagram
2.6.1.2 Run Mode Slave (RMS)
In Run Mode Slave, the receiver is able to continuously scan for incoming data streams.
Detection and validation of a wake-up criterion are not performed, but RUNIN and TSI
are required.
Recognition of TSI and validation of the optional MID (Message IDentification) are done
automatically. The data payload is extracted from the data stream, and moved to the
FIFO.
The various recognition steps are communicated by interrupts. Interrupts can be
generated at frame-start (when a valid TSI has been detected), when a valid MID has
been found and at EOM (End of Message).
Alternatively, a transparent data stream can also be processed externally by the
Application Controller (see Chapter 2.5.1.2 Data Interface).
Run Mode Slave is entered by setting SFR CMC0 bits MSEL to 0 and SLRXEN to 1.
Data Sheet
96
V4.0, 2010-02-19