TDA5240 Datasheet, PDF (57/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
Please note that for Data Slicer Bit Mode a special constellation of RUNIN bits and TSI
bits has to be ensured. Further details can be seen at the end of Chapter 2.4.8.4.
The two independent correlators can be configured in the x_TSIMODE register to work
in one of the following four TSI modes:
16-Bit Mode: As a single correlator of up to 32 chips
The length of the x_TSILENA register must be set to 16d whenever x_TSILENB is higher
than 0.
x_TSILENA = 16d, x_TSILENB = 6d
RunIn
Incoming Pattern ^{0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 0 1 0}
Manchester Coded
TSI Pattern Match
FSYNC
Data into FIFO
01010101011001100101011010101010011001011001
x_TSIPTB
x_TSIPTA
5 4 3 2 1 0 151413121110 9 8 7 6 5 4 3 2 1 0
0110011001010110101010
1010010
Figure 27 16-Bit TSI Mode
8-Bit Parallel Mode: As two correlators of up to 16 chips length each
working simultaneously in parallel
In the following example, TSI Pattern B matches first and generates an FSYNC. The
lengths of both TSI Patterns are now independent from each other. The payload length
for these two TSI Pattern may be different.
x_TSILENA = 16d, x_TSILENB = 6d
RunIn
Incoming Pattern
00000101010010
Manchester Coded
TSI Pattern B Match
FSYNC
Data into FIFO
0101010101100110011001011001
x_TSIPTB
543210
011001
1010010
Figure 28 8-Bit Parallel TSI Mode
Data Sheet
57
V4.0, 2010-02-19