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TDA5240 Datasheet, PDF (179/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver
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TDA5240
Appendix
Register Overview
Table 1 Register Overview (cont’d)
Register Short Name Register Long Name
Offset Address
D_PLLFRAC1C2
D_PLLFRAC2C2
D_PLLINTC3
D_PLLFRAC0C3
D_PLLFRAC1C3
D_PLLFRAC2C3
PLL Fractional Division Ratio Register 1 Channel 2 35FH
PLL Fractional Division Ratio Register 2 Channel 2 360H
PLL MMD Integer Value Register Channel 3
361H
PLL Fractional Division Ratio Register 0 Channel 3 362H
PLL Fractional Division Ratio Register 1 Channel 3 363H
PLL Fractional Division Ratio Register 2 Channel 3 364H
Page Number
Table 2 Register Overview and Reset Value
Register Short Name Register Long Name
Offset Address
Appendix - Registers Chapter, Register Description
A_MID0
A_MID1
A_MID2
A_MID3
A_MID4
A_MID5
A_MID6
A_MID7
A_MID8
A_MID9
A_MID10
A_MID11
A_MID12
A_MID13
A_MID14
A_MID15
A_MID16
A_MID17
A_MID18
A_MID19
A_MIDC0
A_MIDC1
A_IF1
A_WUC
A_WUPAT0
A_WUPAT1
A_WUBCNT
A_WURSSITH1
Message ID Register 0
Message ID Register 1
Message ID Register 2
Message ID Register 3
Message ID Register 4
Message ID Register 5
Message ID Register 6
Message ID Register 7
Message ID Register 8
Message ID Register 9
Message ID Register 10
Message ID Register 11
Message ID Register 12
Message ID Register 13
Message ID Register 14
Message ID Register 15
Message ID Register 16
Message ID Register 17
Message ID Register 18
Message ID Register 19
Message ID Control Register 0
Message ID Control Register 1
IF1 Register
Wake-Up Control Register
Wake-Up Pattern Register 0
Wake-Up Pattern Register 1
Wake-Up Bit or Chip Count Register
RSSI Wake-Up Threshold for Channel 1 Register
000H
001H
002H
003H
004H
005H
006H
007H
008H
009H
00AH
00BH
00CH
00DH
00EH
00FH
010H
011H
012H
013H
014H
015H
016H
017H
018H
019H
01AH
01BH
Reset Value
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
20H
04H
00H
00H
00H
00H
Data Sheet
179
V4.0, 2010-02-19
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