TDA5240 Datasheet, PDF (203/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
WUPMSEL 5
Type
w
WULCUFFB 4
w
UFFBLCOO 3
w
WUCRT
2:0
w
Wake-Up Pattern Register 0
Description
Wake Up Pattern Mode Selection
0_B Chip mode
1_B Bit mode
Reset: 0_H
Select a "Wake Up on Level Criterion", when UFFBLCOO is enabled.
0_B RSSI
automatically selected, when A_CHCFG.EXTPROC = "10"
1_B Signal Recognition
Reset: 0_H
Ultrafast Fall Back to SLEEP or additional Level criterion in
Constant On Off.
Enables additional parallel processing of "Level Criterion", when a "Data
Criterion" is selected in WUCRT.
In case of Fast Fall Back to SLEEP or Permanent Wake-Up Search, this
mode is called UFFB (Ultrafast Fall Back). Same Mode can be used in
Constant On-Off.
0_B Disabled
1_B Enabled
Reset: 0_H
Select a "Wake Up Criterion"
000_B Pattern Detection (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
001_B Random Bits (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
010_B Equal Bits (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
011_B Wake Up on Symbol Sync, Valid Data Rate (Data Criterion); The
A_WUBCNT Register is
not used in this mode
100_B RSSI (Level Criterion)
automatically selected, when A_CHCFG.EXTPROC = "10"
101_B Signal Recognition (Level Criterion)
110_B n.u.
111_B n.u.
Reset: 4_H
A_WUPAT0
Wake-Up Pattern Register 0

Data Sheet
Offset
018_H
:83$7
Z
203
Reset Value
00_H

V4.0, 2010-02-19