TDA5240 Datasheet, PDF (170/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Overview
Table 1 Register Overview (cont’d)
Register Short Name Register Long Name
CMC0
Chip Mode Control Register 0
RSSIPWU
Wakeup Peak Detector Readout Register
IS0
Interrupt Status Register 0
IS1
Interrupt Status Register 1
RFPLLACC
RF PLL Actual Channel and Configuration
Register
RSSIPRX
RSSI Peak Detector Readout Register
RSSIPPL
RSSI Payload Peak Detector Readout Register
PLDLEN
Payload Data Length Register
ADCRESH
ADC Result High Byte Register
ADCRESL
ADC Result Low Byte Register
VACRES
VCO Autocalibration Result Readout Register
AFCOFFSET
AFC Offset Read Register
AGCGAINR
AGC Gain Readout Register
SPIAT
SPI Address Tracer Register
SPIDT
SPI Data Tracer Register
SPICHKSUM
SPI Checksum Register
SN0
Serial Number Register 0
SN1
Serial Number Register 1
SN2
Serial Number Register 2
SN3
Serial Number Register 3
RSSIRX
RSSI Readout Register
RSSIPMF
RSSI Peak Memory Filter Readout Register
SPWR
Signal Power Readout Register
NPWR
Noise Power Readout Register
B_MID0
Message ID Register 0
B_MID1
Message ID Register 1
B_MID2
Message ID Register 2
B_MID3
Message ID Register 3
B_MID4
Message ID Register 4
B_MID5
Message ID Register 5
B_MID6
Message ID Register 6
B_MID7
Message ID Register 7
B_MID8
Message ID Register 8
B_MID9
Message ID Register 9
B_MID10
Message ID Register 10
B_MID11
Message ID Register 11
B_MID12
Message ID Register 12
B_MID13
Message ID Register 13
Offset Address
0A6_H
0A7_H
0A8_H
0A9_H
0AA_H
0AB_H
0AC_H
0AD_H
0AE_H
0AF_H
0B0_H
0B1_H
0B2_H
0B3_H
0B4_H
0B5_H
0B6_H
0B7_H
0B8_H
0B9_H
0BA_H
0BB_H
0BC_H
0BD_H
100_H
101_H
102_H
103_H
104_H
105_H
106_H
107_H
108_H
109_H
10A_H
10B_H
10C_H
10D_H
Page Number
270
271
271
272
274
275
275
275
276
276
277
277
278
278
279
279
280
280
280
281
281
281
282
282
Data Sheet
170
V4.0, 2010-02-19