TDA5240 Datasheet, PDF (231/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description





8186('
'5/,0(1
581/(1

Z
Z
Field
Bits
UNUSED
7:3
DRLIMEN
2
Type
-
w
RUNLEN
1:0
w
CDR DC Chip Tolerance Register
Description
UNUSED
Reset: 00_H
Enable data rate error acceptance limitation.
The limits are defined in CDRDRTHRP and CDRDRTHRN registers.
0_B Disabled
1_B Enabled
Reset: 0_H
RUNIN Length. The RUNIN length is equal to PLL-start-value
calculation time. This means
that the shorter RUNIN length decreases the data rate offset calculation
accuracy and symbol synchronization found signal generation stability.
Note that the RUNLEN have to be changed together with the TSI
configuration registers.
00_B 8 chips
01_B 7 chips
10_B 6 chips
11_B 5 chips
Reset: 1_H
A_CDRTOLC
CDR DC Chip Tolerance Register



8186('

Offset
049_H

72/&+,3+
Z
Reset Value
0C_H


72/&+,3/
Z
Field
Bits
UNUSED
7:6
TOLCHIPH 5:3
Type
-
w
Description
UNUSED
Reset: 0_H
Duty Cycle Tolerance for Chip Border High Level. Represents the
number of 1/16 bit sample deviation from the ideal chip border
where an edge can occur in direction to the following chip border.
Reset: 1_H
Data Sheet
231
V4.0, 2010-02-19