TDA5240 Datasheet, PDF (171/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Overview
Table 1 Register Overview (cont’d)
Register Short Name Register Long Name
Offset Address
B_MID14
B_MID15
B_MID16
B_MID17
B_MID18
B_MID19
B_MIDC0
B_MIDC1
B_IF1
B_WUC
B_WUPAT0
B_WUPAT1
B_WUBCNT
B_WURSSITH1
B_WURSSIBL1
Message ID Register 14
Message ID Register 15
Message ID Register 16
Message ID Register 17
Message ID Register 18
Message ID Register 19
Message ID Control Register 0
Message ID Control Register 1
IF1 Register
Wake-Up Control Register
Wake-Up Pattern Register 0
Wake-Up Pattern Register 1
Wake-Up Bit or Chip Count Register
RSSI Wake-Up Threshold for Channel 1 Register
RSSI Wake-Up Blocking Level Low Channel 1
Register
10E_H
10F_H
110_H
111_H
112_H
113_H
114_H
115_H
116_H
117_H
118_H
119_H
11A_H
11B_H
11C_H
B_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
11D_H
B_WURSSITH2
B_WURSSIBL2
RSSI Wake-Up Threshold for Channel 2 Register 11E_H
RSSI Wake-Up Blocking Level Low Channel 2
Register
11F_H
B_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
120_H
B_WURSSITH3
B_WURSSIBL3
RSSI Wake-Up Threshold for Channel 3 Register 121_H
RSSI Wake-Up Blocking Level Low Channel 3
Register
122_H
B_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
123_H
B_SIGDETSAT
B_WULOT
B_SYSRCTO
B_TOTIM_SYNC
B_TOTIM_TSI
B_TOTIM_EOM
B_AFCLIMIT
B_AFCAGCD
B_AFCSFCFG
B_AFCK1CFG0
B_AFCK1CFG1
B_AFCK2CFG0
Signal Detector Saturation Threshold Register
Wake-Up on Level Observation Time Register
Synchronization Search Time-Out Register
SYNC Timeout Timer Register
TSI Timeout Timer Register
EOM Timeout Timer Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
124_H
125_H
126_H
127_H
128_H
129_H
12A_H
12B_H
12C_H
12D_H
12E_H
12F_H
Page Number
Data Sheet
171
V4.0, 2010-02-19