TDA5240 Datasheet, PDF (246/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description





8186('
3//)&20
3&
3//)5$&&

Z
Z
Field
Bits
UNUSED
7:6
PLLFCOMPC3 5
PLLFRAC2C3 4:0
Type
-
w
w
Description
UNUSED
Reset: 0_H
Fractional Spurii Compensation enable for Channel 3
0_B Disabled
1_B Enabled
Reset: 0_H
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09_H
Special Function Register Page Register
SFRPAGE
Special Function Register Page Register

8186('

Offset
080_H
Reset Value
00_H



6)53$*(
Z
Field
Bits
UNUSED
7:2
SFRPAGE 1:0
Type
-
w
Description
UNUSED
Reset: 00_H
Selection of Register Page File (Configuration A..D) for SPI
communication
00_B Page 0 (Config. A, start address: 000_H)
01_B Page 1 (Config. B, start address: 100_H)
10_B Page 2 (Config. C, start address: 200_H)
11_B Page 3 (Config. D, start address: 300_H)
Reset: 0_H
PP0 and PP1 Configuration Register
PPCFG0
PP0 and PP1 Configuration Register
Data Sheet
Offset
081_H
246
Reset Value
50_H
V4.0, 2010-02-19