TDA5240 Datasheet, PDF (84/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
FIFO Status Word
The FIFO Status Word is attached at the end of a FIFO SPI transmission, and shows if
there was an overflow, and how many valid data bits were transmitted. The number of
valid FIFO bits is indicated at bit positions S0 to S5. S6 of the Status Word is always
undefined.
SDI
I7 I6
SDO
high impedance Z
I1 I0
32 FIFO Bits
Status Word
D0 D1
D30 D31 S7 S6
S1 S0
Figure 55 SPI Data FIFO Read
If the Write Address Pointer outruns the Read Address Pointer, an overflow is indicated
in the FIFO Overflow Status bit in the FIFO Read Status Word at position S7. All 32 FIFO
bits and the bits S5 to S0 of the Status Word are undefined while the Overflow Status bit
is set.
If a TSI is detected after an overflow, the FIFO Overflow Status bit is cleared and the
entire receive FIFO is initialized.
Initialization
Additionally, there are two possibilities to initialize the receive FIFO.
• If the INITFIFO bit is set in the CMC1 register (“Init FIFO at Cycle Start”) the entire
receive FIFO is always initialized
a.) after switching to Run Mode Slave or
b.) switching from Self Polling Mode to Run Mode Self Polling.
• If the FSINITFIFO bit in CMC1 register is set, the entire receive FIFO is initialized
when a TSI is detected and the receive FIFO is not locked (“Init FIFO at Frame
Start”).
Last received message length
For application protocols with several payload frames and only a short pause in-
between, the microcontroller would have to read out the FIFO very fast after detection of
an EOM. Thus even slow or overloaded Application Controllers have the possibility now
to determine the end of the last message, when reading out the FIFO, while the next
payload frame gets already received and payload data is further stored in the FIFO.
Data Sheet
84
V4.0, 2010-02-19