TDA5240 Datasheet, PDF (282/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver


566,30)
U
Field
Bits
RSSIPMF
7:0
Type
r
Signal Power Readout Register
Description
RSSI Peak Memory Filter Level
Reset: 00_H
TDA5240
Appendix
Register Description

SPWR
Signal Power Readout Register

Offset
0BC_H
63:5
U
Reset Value
00_H

Field
SPWR
Bits
Type
7:0
r
Noise Power Readout Register
Description
Signal Power
The register contains the actual signal power which should be used to
calculate the value of x_SIGDET0, x_SIGDET1 and x_SIGDETLO
registers
Reset: 00_H
NPWR
Noise Power Readout Register

Offset
0BD_H
13:5
U
Reset Value
00_H

Data Sheet
282
V4.0, 2010-02-19