TDA5240 Datasheet, PDF (43/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
2.4.8.3 Clock and Data Recovery
An all-digital PLL (ADPLL) recovers the data clock from the incoming data stream. The
second main function is the generation of a signal indicating symbol synchronization.
Synchronization on the incoming data stream generally occurs within the first 4 bits of a
telegram.
Tnom / 16
from Clock
Recovery Slicer
Timing Extrapolation
EOM
Phase
Detector
PI
Loop Filter
Digital
Controlled
Oscillator
Symbol
Sync found
Recovered
Clock
T_nom / 2
T_nom / 2
Figure 19 Clock Recovery (ADPLL)
Clock Recovery is implemented as standard ADPLL PI regulator with Timing
Extrapolation Unit for fast settling.
In the unlocked state, the Timing Extrapolation Unit calculates the frequency offset for
the incoming data stream. If the defined number of Bi-phase encoded bits are detected
(the RUNIN length can be set in the x_CDRRI register), the I-part and the PLL oscillator
will be set and the PLL will be locked.
When x_CDRRI.RUNLEN is set to small values, then the I-part is less accurate (residual
error) and can lead to a longer needed PLL settling time and worse performance in the
Data Sheet
43
V4.0, 2010-02-19