TDA5240 Datasheet, PDF (273/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
IS1
Interrupt Status Register 1

(20'
UF

0,')'
UF

)6<1&'
UF
Offset
0A9_H

:8'
UF

(20&
UF

0,')&
UF
Reset Value
FF_H

)6<1&&
UF

:8&
UF
Field
Bits
EOMD
7
MIDFD
6
FSYNCD
5
WUD
4
EOMC
3
MIDFC
2
FSYNCC
1
Type
rc
rc
rc
rc
rc
rc
rc
Description
Interrupt Request by "End of Message" from Configuration D (Reset
event sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Interrupt Request by "Message ID Found" from Configuration D
(Reset event sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Interrupt Request by "Frame Sync" from Configuration D (Reset
event sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Interrupt Request by "Wake Up" from Configuration D (Reset event
sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Interrupt Request by "End of Message" from Configuration C (Reset
event sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Interrupt Request by "Message ID Found" from Configuration C
(Reset event sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Interrupt Request by "Frame Sync" from Configuration C (Reset
event sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Data Sheet
273
V4.0, 2010-02-19