TDA5240 Datasheet, PDF (46/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
Duty Cycle Variation
Ideally, the input signal to the Clock and Data Recovery (CDR) would have a chip width
of 8 samples and a bit width of 16 samples and the CDR would not lock onto any input
that violates this. However, due to variations in the duty cycle this stringent assumption
for the pulse widths will in general not be true. Therefore it is necessary to loosen this
requirement by using tolerance windows.
TOLCHIPH
TOLCHIPL
TOLBITL
TOLBITH
1
t
lim_chip_low = 8 - TOLCHIPL
lim_bit_low = 16 - TOLBITL
lim_chip_high = 8 + TOLCHIPH
lim_bit_high = 16 + TOLBITH
Figure 21 Definition of Tolerance Windows for the CDR
There exist now two registers - x_CDRTOLC for the chip width tolerance and
x_CDRTOLB for the bit width tolerance - that can be used to tighten or loosen the
windows around the ideal pulse widths. As it can easily be seen from Figure 21, tighter
windows will result in more stringent requirements for the input data to have a 50% duty
cycle and bigger windows will allow the duty cycle to vary more. Figure 21 also depicts
the meaning of the bits in the registers x_CDRTOLC and x_CDRTOLB.
Data Sheet
46
V4.0, 2010-02-19