TDA5240 Datasheet, PDF (127/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
2.8
Digital Control (SFR Registers)
Functional Description
2.8.1 SFR Address Paging
An SPI instruction allows a maximum address space of 8 bit. The address space for
supporting more than one configuration set is exceeding this 8 bit address room.
Therefore a page switch is introduced, which can be applied via register SFRPAGE (see
Figure 92).
0x000
logical address space
0
Configuration A ¹⁾ - Page 0
d
physical address space
Configuration A ¹⁾ - Page 0
0x080
0x0FF
0x100
Reserved ²⁾
Common Registers ³⁾
Reserved ⁴⁾
Configuration B ¹⁾ - Page 1
128 _d
255 _d
256 _d
Reserved ²⁾
Common Registers ³⁾
Reserved ⁴⁾
Configuration B ¹⁾ - Page 1
0x180
0x1FF
0x200
Reserved ²⁾
Common Registers ³⁾
Reserved ⁴⁾
Configuration C ¹⁾ - Page 2
384 _d
511 _d
512 _d
Reserved ²⁾
Configuration C ¹⁾ - Page 2
0x280
0x2FF
0x300
Reserved ²⁾
Common Registers ³⁾
Reserved ⁴⁾
Configuration D ¹⁾ - Page 3
640 _d
767 _d
768 _d
Reserved ²⁾
Configuration D ¹⁾ - Page 3
Figure 92
0x380
0x3FF
Reserved ²⁾
Common Registers ³⁾
Reserved ⁴⁾
896 _d
1023 _d
Reserved ²⁾
1) _{Configuration dependent register block (4 protocol specific sets)}
page switch via SFRPAGE register
2), 4) _{Reserved – Forbidden area}
3) _{Configuration independent registers (common for all configurations )}
map (“mirror“ ) to the same physical address space
SFR Address Paging
2.8.2 SFR Register List and Detailed SFR Description
The register list is attached in the Appendix at the end of the document.
Registers for Configurations B, C and D are equivalent and not shown in detail.
All registers with prefix “A_” are related to Configuration A. All these registers are also
available for Configuration B, C and D having the prefix “B_”, “C_” and “D_”.
Data Sheet
127
V4.0, 2010-02-19