TDA5240 Datasheet, PDF (206/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description


:8566,%/
Z
Field
Bits
WURSSIBL1 7:0
Type
w
Description
Wake Up on RSSI Blocking Level LOW for Channel 1
Reset: FF_H
RSSI Wake-Up Blocking Level High Channel 1 Register
A_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel
1 Register
Offset
01D_H

:8566,%+
Z
Reset Value
00_H

Field
Bits
WURSSIBH1 7:0
Type
w
Description
Wake Up on RSSI Blocking Level HIGH for Channel 1, when RSSI is
selected as WU criterion or FFB criterion.
In case of Signal Recognition as WU criterion or FFB criterion, the
register defines the minimum consecutive T/16 samples of the Signal
Recognition output to be at high level for a positive wake up event
generation or FFB generation
Reset: 00_H
RSSI Wake-Up Threshold for Channel 2 Register
A_WURSSITH2
RSSI Wake-Up Threshold for Channel 2
Register

Offset
01E_H
:8566,7+
Z
Reset Value
00_H

Data Sheet
206
V4.0, 2010-02-19