TDA5240 Datasheet, PDF (205/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
WUBCNT
6:0
Type
w
Description
Wake Up Bit/Chip Count Register (unit is bits; only exception is WU
Pattern Chip Mode, where unit is chips, see A_WUC.WUPMSEL)
Counter Register to define the maximum counts of bits/chips for Wake Up
detection.
Min: 00h = 0 Bits/Chips to count
In Random Bits or Equal Bits Mode this will cause a Wake Up
on Data Criterion immediately after Symbol Synchronization is found.
In Pattern Detection Mode this will cause no Wake Up on Data Criterion.
In this
Mode there is needed minimum 11h = 17 Bits/Chips to shift
one Pattern through the whole Pattern Detector. Because
comparision can only be started when at least the comparision
register is completely filled.
Max: 7Fh: 127 Bits/Chips to count after Symbol Sync found
Reset: 00_H
RSSI Wake-Up Threshold for Channel 1 Register
A_WURSSITH1
RSSI Wake-Up Threshold for Channel 1
Register

Offset
01B_H
:8566,7+
Z
Reset Value
00_H

Field
Bits
WURSSITH1 7:0
Type
w
Description
Wake Up on RSSI Threshold level for Channel 1
Wake Up Request generated when actual RSSI level is above this
threshold
Reset: 00_H
RSSI Wake-Up Blocking Level Low Channel 1 Register
A_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
Offset
01C_H
Reset Value
FF_H
Data Sheet
205
V4.0, 2010-02-19