TDA5240 Datasheet, PDF (243/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
UNUSED
7:6
PLLINTC2
5:0
Type
-
w
Description
UNUSED
Reset: 0_H
SDPLL Multi Modulus Divider Integer Offset value for Channel 2
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13_H
PLL Fractional Division Ratio Register 0 Channel 2
A_PLLFRAC0C2
PLL Fractional Division Ratio Register 0
Channel 2
Offset
05E_H

3//)5$&&
Z
Reset Value
F3_H

Field
Bits
PLLFRAC0C2 7:0
Type
w
Description
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 2
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3_H
PLL Fractional Division Ratio Register 1 Channel 2
A_PLLFRAC1C2
PLL Fractional Division Ratio Register 1
Channel 2
Offset
05F_H

3//)5$&&
Z
Reset Value
07_H

Field
Bits
PLLFRAC1C2 7:0
Type
w
Description
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 2
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07_H
Data Sheet
243
V4.0, 2010-02-19