TDA5240 Datasheet, PDF (79/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
In default mode the CH_STR signal is active high and has a delay of T_CHIP/8 relative to
the data chip and a duration of T_CHIP/2. The polarity of the CH_STR signal is
programmable, this can be done via PPCFG2 register.
CH_DATA
D_n
D_n+1
CH_STR
TCHIP/8
TCHIP/2
Figure 50 Timing of the Transparent Mode - Chip Data and Strobe
Transparent Mode - Matched Filter (TMMF)
The received data after the Matched Filter (Two-Chip Matched Filter) with an additional
SIGN function is provided via the DATA_MATCHFIL signal (PPx pin). In this mode
sensitivity measurements with ideal data clock can be performed very simple. For further
details see the block diagram in Figure 15.
Sensitivity in this transparent mode is significantly depending on the implemented clock
and data recovery algorithm of the user software in the application controller.
TDA5240
data
interface
RX data
scheduler
Figure 51 Data interface for the Transparent Modes TMMF / TMRDS
Transparent Mode - Raw Data Slicer (TMRDS)
This mode supports processing of data even without bi-phase encoding (e.g. NRZ
coding) by providing the received data via the One-Chip Matched Filter on the DATA
signal (PPx pin). See more details in the block diagram in Figure 15.
Data Sheet
79
V4.0, 2010-02-19