TDA5240 Datasheet, PDF (219/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

AGC Threshold Register
TDA5240
Appendix
Register Description
A_AGCTHR
AGC Threshold Register

$*&783
Z
Offset
035_H


$*&7/2
Z
Reset Value
08_H

Field
Bits
AGCTUP
7:4
AGCTLO
3:0
Type
w
w
Description
AGC Upper Attack Threshold [dB]
AGC Upper Threshold = A_AGCCFG1.AGCTHOFFS + 25.6 +
AGCTUP*1.6
Reset: 0_H
AGC Lower Attack Threshold [dB]
AGC Lower Threshold = A_AGCCFG1.AGCTHOFFS + AGCTLO*1.6
Reset: 8_H
Digital Receiver Configuration Register
A_DIGRXC
Digital Receiver Configuration Register
Offset
036_H
Reset Value
40_H

,1,7'5;
(6
Z

,1,7)5&
6
Z


&2'(
Z

&+,3',1
9
Z

',19(;7
Z

$$)%<3
Z

$$))&6(
/
Z
Field
Bits
INITDRXES 7
INITFRCS
6
Type
w
w
Description
Init the Digital Receiver at EOM or Loss of Symbol Sync (e.g. for
initialization of the Peak Memory Filter)
0_B Disabled
1_B Enabled
Reset: 0_H
Init the Framer at Cycle Start in RMSP.
If disabled, the WUP Data can be used as part of TSI as well in case the
modulation type is the same for SPM and RMSP
0_B Disabled
1_B Enabled
Reset: 1_H
Data Sheet
219
V4.0, 2010-02-19