TDA5240 Datasheet, PDF (245/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
A_PLLFRAC0C3
PLL Fractional Division Ratio Register 0
Channel 3
Offset
062_H

3//)5$&&
Z
Reset Value
F3_H

Field
Bits
PLLFRAC0C3 7:0
Type
w
Description
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3_H
PLL Fractional Division Ratio Register 1 Channel 3
A_PLLFRAC1C3
PLL Fractional Division Ratio Register 1
Channel 3
Offset
063_H

3//)5$&&
Z
Reset Value
07_H

Field
Bits
PLLFRAC1C3 7:0
Type
w
Description
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07_H
PLL Fractional Division Ratio Register 2 Channel 3
A_PLLFRAC2C3
PLL Fractional Division Ratio Register 2
Channel 3
Offset
064_H
Reset Value
09_H
Data Sheet
245
V4.0, 2010-02-19