TDA5240 Datasheet, PDF (207/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
WURSSITH2 7:0
Type
w
Description
Wake Up on RSSI Threshold level for Channel 2
Wake Up Request generated when actual RSSI level is above this
threshold
Reset: 00_H
RSSI Wake-Up Blocking Level Low Channel 2 Register
A_WURSSIBL2
RSSI Wake-Up Blocking Level Low Channel 2
Register
Offset
01F_H

:8566,%/
Z
Reset Value
FF_H

Field
Bits
WURSSIBL2 7:0
Type
w
Description
Wake Up on RSSI Blocking Level LOW for Channel 2
Reset: FF_H
RSSI Wake-Up Blocking Level High Channel 2 Register
A_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel
2 Register
Offset
020_H

:8566,%+
Z
Reset Value
00_H

Field
Bits
WURSSIBH2 7:0
Type
w
Description
Wake Up on RSSI Blocking Level HIGH for Channel 2, when RSSI is
selected as WU criterion or FFB criterion.
In case of Signal Recognition as WU criterion or FFB criterion, the
register defines the minimum consecutive T/16 samples of the Signal
Recognition output to be at high level for a positive wake up event
generation or FFB generation
Reset: 00_H
Data Sheet
207
V4.0, 2010-02-19