TDA5240 Datasheet, PDF (49/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
In bit mode the data slicer has only one threshold (zero) to distinguish between the two
levels of the matched filter output. The data slicer internally maps a positive value to a 1
and a negative value to a -1. After that, the selected line decoding is applied.
Summary of data slicer modes in the TDA5240:
Data Slicer Chip mode:
• Code violations detectable (TSI, or EOM)
• Performance loss compared to bit mode
• Activation via setting register x_SLCCFG to a value of
+ 0x90 (Chip Mode EOM-CV: For patterns with code violations in data packet and
optimized for activated EOM code violation criterion (and optional EOM data
length criterion))
+ 0x94 (Chip Mode EOM-Data length: For patterns with code violations in data
packet and optimized for activated EOM data length criterion only)
+ 0x95 (Chip Mode Transparent: When Framer is not used, but CH_DATA /
CH_STR are used for data processing)
Data Slicer Bit mode:
• No code violations detectable
• Full performance
• In case of Bi-phase mark and Bi-phase space an additional bit must be sent to ensure
correct decoding of the last bit
• Activation via setting register x_SLCCFG to a value of 0x75
In Data Slicer Bit mode an even number of TSI chips needs to be used.
When Data Slicer Bit mode is selected, then the the last chip of RUNIN must be different
from first chip of TSI (e.g. Runin-bit sequence 000000 and TSI bit sequence 0xx...xxx is
OK). Otherwise the TSI will not be detected correctly.
On using Data Slicer Bit Mode, the Wake-up criteria Equal Bits Detection and Pattern
Detection cannot be applied.
A line decoder decodes the incoming data chips according to the encoding scheme (see
Chapter 2.4.8.2).
Data Sheet
49
V4.0, 2010-02-19