TDA5240 Datasheet, PDF (47/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
Data Rate Acceptance Limitation
The Clock and Data Recovery is able to accept data rate errors of more than +/-15% with
a certain loss of performance. There exist Multi-Configuration applications where the
data rate of both configurations are within this range. So the adjacent data rates of these
configurations are disturbing each other. The limitation of the data rate acceptance can
be activated in this case.
clock recovery
slicer
symbol synchronization
preset value correlator
CLOCK RECOVERY
Data Rate
Acceptance
&
Limitation
cdr_lock
Clock Recovery PLL
cdr_clock
Figure 22 Data Rate Acceptance Limitation
The clock and data recovery (CDR) regenerates the clock based on the input data
delivered from the clock recovery (CR) slicer. Symbol synchronization (cdr_lock) is
achieved when a specified number of chips (can be set via register x_CDRRI.RUNLEN)
has a valid pulse width. In parallel the preset value correlator estimates a preset value
for the clock recovery PLL so that a shorter settling time is achieved. This preset value
is also proportional to the data rate and is therefore used in the data rate acceptance
limitation block. If the preset value is outside a certain range (positive and negative
threshold configurable via registers CDRDRTHRP and CDRDRTHRN), the CDR does
not go into lock and no symbol synchronization is generated.
For each configuration there exists one bit (register x_CDRRI.DRLIMEN) to switch the
data rate acceptance limitation functionality on or off. Data rate acceptance limitation is
disabled by default. All configurations share the same threshold registers, the default
Data Sheet
47
V4.0, 2010-02-19