TDA5240 Datasheet, PDF (62/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
Please note that after a gap, the internal TSI comparison register is cleared (all chips set
to ’0’). In this case, a TSI B criteria of “0000” would always match at the beginning. To
avoid such an unwanted matching, set the highest TSI B match chip to ’1’.
RunIn
TSIA
TSIGAP=10 chips ^GapSync
TSIB
Incoming Pattern[bits] ... 0 0 1 0 S _ _ _ _ _ 0 0 0 0 1 0 0 0 1 1 1 1 1
TSIBstart
123456789012345678901234567890123456
Start of TSIB
comparison
Stop of TSIB
comparison
Figure 33 TSIGap TSIB Timing
The TVWIN (Timing Violation WINdow) and TSIGAP dependency is shown in Figure 34.
TVWIN
CV
TVWIN
TSIA
int .
delay
GAP
TVWIN
RUNIN/
TSIGRSYN = 1
TVWIN without GAP
TVWIN with GAP
Figure 34 TVWIN and TSIGAP dependency example
TVWIN calculation for pattern without Gap time:
TVWIN = round((8 + 16 ⋅ CV + 8) ⋅ 1.25)
The entire TVWIN time is made up of the CV¹⁾ number itself, the half bit before CV and
the half bit after the CV. To reach all frequency and duty cycle errors, 25% of the overall
sum must be added.
TVWIN calculation with Gap time:
TVWIN = round(max{((8 + 16 ⋅ CV + 8) ⋅ 1.25), (8 + 16 ⋅ TSIA_CV + 16 ⋅ 1 + 8) ⋅ 1.25})
1) CV...number of bits containing manchester code violations
Data Sheet
62
V4.0, 2010-02-19